NXP Semiconductors /MIMXRT1021 /USDHC1 /CLK_TUNE_CTRL_STATUS

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Interpret as CLK_TUNE_CTRL_STATUS

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DLY_CELL_SET_POST 0DLY_CELL_SET_OUT 0DLY_CELL_SET_PRE 0 (NXT_ERR)NXT_ERR 0TAP_SEL_POST 0TAP_SEL_OUT 0TAP_SEL_PRE0 (PRE_ERR)PRE_ERR

Description

CLK Tuning Control and Status

Fields

DLY_CELL_SET_POST

Delay cells on the feedback clock between CLK_OUT and CLK_POST

DLY_CELL_SET_OUT

Delay cells on the feedback clock between CLK_PRE and CLK_OUT

DLY_CELL_SET_PRE

delay cells on the feedback clock between the feedback clock and CLK_PRE

NXT_ERR

NXT error

TAP_SEL_POST

Delay cells added on the feedback clock between CLK_OUT and CLK_POST

TAP_SEL_OUT

Delay cells added on the feedback clock between CLK_PRE and CLK_OUT

TAP_SEL_PRE

TAP_SEL_PRE

PRE_ERR

PRE error

Links

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